C&T Solution CT-MSB01 Uživatelský manuál stáhnout pdf (Strana 37)

CT-MHW0X Intel 4th Gen Core Processor i7/i5/i3/Pentium/Celeron Micro-ATX IMB

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Index Port

0xA00

Data Port

0xA01

4.13.1.2 Registers Description

4.13.1.2.1 GPIO Output Data Select

 GPIO Output Data Register

(Index port=0xA00, Data port=0xA01, Offset=0x89)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

GPO3

GPO2

GPO1

GPO0

Note.

Bit X = 0 outputs 0 when in output mode

Bit X = 1 outputs 1 when in output mode

4.13.1.3 PSUEDO CODE

Example1 Set GPO1 to output LOW

Step1: WriteIOByte8(0xA00,0x89) //Write configuration offset into index port

Step2: ByteData = ReadIOByte8(0xA01) //Read data from data port

Step3: ByteData = ByteData & 0xDF //Set Bit5 to 0 (output LOW)

Step4: WriteIOByte8(0xA01, ByteData) //Write back this change

4.14 Watchdog Timer

4.14.1 Board Design

The WDT (Watchdog Timer) is implemented by using Fintek F81866A.

Address

WDT Base Address

0xA10

4.14.2 PSUEDO CODE

 Set WDT Time Unit (Second Unit)

Step1: ByteData = ReadIOByte(0xA15) //Read current setting

Step2: ByteData = ByteData & 0xF7 //Set time unit to “second”

Step3: WriteIOByte(0xA15, ByteData) //Write back

 Set WDT Time Value

Step1: WriteIOByte(0xA16, Time) //Set watch dog time value

1 2 ... 32 33 34 35 36 37 38 39 40 41 42 ... 89 90

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